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pd671xxx - 8 / 12 / 24-channel poe af and at dimm data sheet (non-confidential) description key features microsemi?s? new and unique fam ily of power over ethernet (poe) modules enable next-gener ation network devices to share data and power over the same cable. the pd671xxx poe pse modules are fit / form compatible with the standard plug-in memory modules used in personal computers (dual inline memory modules - dimms) (see figure 1 and figure 12). thus, the use of these modules permit network devices to be designed for up to 96 ports, with fewer ports actually installed. additional modules can be inserted in the field at any time. the pd671xxx (8, 12 or 24 ports dimm) includes a wide range of functions. some of these modules include the pd69000 micro-controller unit (poe cont roller) for enhanced features and a flexible work environment in a dimm master or dimm slave configuration (refer to ordering information, page 2). microsemi?s poe pd671xxx dimms implement real time mechanisms including detection, cl assification, port real-time protection and system level functions (power management and mib support). microsemi?s pd69012 ic, 12-channel poe manager ic is at the heart of these modules. pd671xxx dimms enable the detection of ieee802.3at-2009 ty pe 1 (low power) or type 2 (high power) powered devices (pds), ensuring safe power feeding and removal over ethernet ports. the pd69012-based dimms detect and disable disconnected ports, using dc or ac disconnection methods. the dimms are embedded in multi- port and highly populated ethernet switches, requiring a minimum of external components. the pd671xxx dimm is fully backwards compatible with the pd670xx dimm and can be dropped into existing designs. figure 1: poe pd67124 dimm important: for the most current data, consult microsemi?s website: http://www.microsemi.com ? ieee 802.3at-2009 and ieee802.3af-2003 compliant ? up to 30 w per port power poe solution ? rohs compliant ? supports ietf poe mib (rfc 3621) ? up to 24 power ports per single dimm ? up to 96 ports in a system, using master and slave configuration ? thermal protection per port ? thermal monitoring capabilities ? pre-standard detection methods (cisco inline power and power over lan legacy) ? non-standard terminals supported ? dc disconnect with dc modulation ? ac disconnect function utilizing external diodes ? pd 2-events classification function ? operates using a single input (44 to 57 vdc) ? i 2 c or uart host interface ? host communicat ion is backward compatible with pd67024m communication, or marvell? issr ? programmable over current protection per port ? built-in power management algorithm ? internal power-on reset mechanism ? fast port shutdown on power supply failure ? supports backplane power management ? automatic on/off sequencer for 96 ports ? disable/enable power per port ? continuous port current monitoring ? serial interface for led indicator support ? backwards compatible with pd670xx ? fit/form compliant with168-pin dimm jedec mo-161f, 3.3 v ? space efficient compact design ? factory pre-tested, for plug-and-play integration ? safety standard compliant: ul / cul per ul60950-1 (mounted on microsemi evaluation board)
pd671xxx - 8 / 12 / 24-channel poe af and at dimm data sheet (non-confidential) copyright ? 2009 microsemi page 2 rev. 1.0 / 17-march-10 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; within the usa: (8 00) 713-4113, outside the usa: (949) 221-7100 fax: (949) 756-0308 www. microsemi . com pd671xx dimm ordering information part number ports port disconnect method dimm master/slave mode enhanced/auto [3] pd67124mdc-gggg [1] 24 dc master enhanced pd67124s 24 ac/dc [4] slave [2] enhanced pd67112mdc-gggg 12 dc master enhanced pd67108mdc-gggg 8 dc master enhanced pd67124mac-gggg 24 ac master enhanced pd67112mac-gggg 12 ac master enhanced PD67108MAC-GGGG 8 ac master enhanced pd67124am 24 ac/dc [5] master auto pd67124as 24 ac/dc [5] slave [2] auto pd67112am 12 ac/dc [5] master auto pd67108am 8 ac/dc [5] master auto note : [1] ? gggg: mcu software version. [2] ? dimm slave should be used in c onjunction with dimm master (for systems require more than 24 ports). [3] ? enhanced and auto mode of operation stand for the poe syst em features. the enhanced mode system includes the pd69000 poe controller. [4] ? dimm slave port disconnection method is determi ned by the dimm master which controllers it. [5] ? dimm functioning at the auto mode configuration can be c onfigured to ac or dc port disconnection method by the system hos t. further details can be found in the auto mode user guide, catalogue number 06-1200-056. applicable documents ? ieee 802.3at-2009 standa rd, dte power via mdi ? pd69012 data sheet, catalogue number 06-0069-058 ? pd69000 data sheet, catalogue number 06-0070-058 ? serial communication protocol user guide 06-0032-056 ? auto mode user guide, catalogue number 06-1200-056 ? layout design guidelines for dimm-based poe systems, an-132 catalogue number 06-0010-080 ? designing a dimm-based poe system, an-133 catalogue number 06-0011-080 ?
pd671xxx - 8 / 12 / 24-channel poe af and at dimm data sheet (non-confidential) copyright ? 2009 microsemi page 3 rev. 1.0 / 17-march-10 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; within the usa: (8 00) 713-4113, outside the usa: (949) 221-7100 fax: (949) 756-0308 www. microsemi . com pd671xx dimm absolute maximum ratings vmain -0.3 to 80 vdc (1 ) dgnd, agnd, qgnd -0.3 to 0.3 vdc (2 ) vport_posx, vport_negx - 0.3 to 80 vdc (1 ) 3 _ 3 vout 3.8 vdc ext_reg - 0.3 to 6 vdc i 2 c_addr_m. -0.3 to (3_3vout + 0.3 vdc) miso, mosi, sck, cs, scl, sd a, ssn, led_cs, asic_reset -0.3 to (3_3vout + 0.3 vdc) esd (human body model) 2 kv (3 ) storage temperature -40 to +125 c notes : ?x? defines port numbers, 0 to 11, inclusive. (1) 80 vdc is the transient voltage that can be applied for up to one minute. (2) maximum voltage value between grounds. (3) esd human body model is: (czap = 100 pf, rzap = 1500 ? ). stresses beyond those listed above can cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods could affect device reliability. calculated mtbf data [1] operation mode failures per 10^6 hours mtbf(hours) pd67124m @ 25c ambient ieee 802.3at-2009 0.5181 1930000 pd67124m @ 25c ambient ieee802.3af-2003 0.5128 1950000 notes : [1] ? mtbf calculation made for the worst case poe dimm populated with 24 fully loaded ports
pd671xxx - 8 / 12 / 24-channel poe af and at dimm data sheet (non-confidential) copyright ? 2009 microsemi page 4 rev. 1.0 / 17-march-10 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; within the usa: (8 00) 713-4113, outside the usa: (949) 221-7100 fax: (949) 756-0308 www. microsemi . com pd671xx dimm operating conditions parameter min. nom. max. unit operating ambient temperature -10 +70 c operating voltage (see figure 2) 40 to 44 44 to 55 55 to 57 vdc operating humidity (non-condensi ng, per iec 68-2-56) 95 % notes : operating functions depend on the input voltage. operating voltage range for ieee802.3af is 44 to 57 vdc operating voltage range for ieee802.3at (high power) is 50 to 57 vdc figure 2: operational voltage ranges airflow to prevent overheating, the application designer sh ould supply a minimal airflow to the pd671xxx dimms. figure 3 shows the power handling capability versus air velo cities in meter/second, as measured at all points of the dimm envelope, prior to insertion into the connector(s). as shown in figure 12, the connectors are spaced by 35 mm; 1 m/s = 197 lfm (linear feet per minute). maximum allowed temperature is +85 c for the mcu (pd69000) and +125 c for the pd69012. air flow 0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 a mbient temperature power per port 0m/s 0.5m/s 1m/s figure 3: power per port for two dimms (48 ports)
pd671xxx - 8 / 12 / 24-channel poe af and at dimm data sheet (non-confidential) copyright ? 2009 microsemi page 5 rev. 1.0 / 17-march-10 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; within the usa: (8 00) 713-4113, outside the usa: (949) 221-7100 fax: (949) 756-0308 www. microsemi . com pd671xx dimm electrical characteristics ________________ _________________ the following sections detail the dc and analog characteristics. dc characteristics for digi tal inputs and outputs parameter symbol min. max. unit remarks pin name scl, xdisable_ports, rx (without in ternal pull-up/pull-down resistor) type schmitt trigger cmos input, ttl level high level input voltage v ih 2.0 v low level input voltage v il 0.8 v input voltage hysteresis 0.3 v input high current i ih -1 +1 a input low current i il -1 +1 a pin name mosi, miso, cs, tx (without internal pull-up/down resistor) sck (with internal resistor) type cmos i/o, ttl level high level input voltage v ih 2.0 v low level input voltage v il 0.8 v input voltage hysteresis 0.3 v input high current i ih -1 +1 a input low current i il -1 +1 a high level output voltage v peri -0.4v v i out = 3 ma low level output voltage 0.4 v i out = 3 ma tri state output current -1 +1 a pin name xasic_reset (with internal resistor) sda (without internal resistor) type cmos open drain output with schmitt trigger input, ttl level high level input voltage v ih 2.0 v low level output voltage v oh 0.4 v i out = 3ma low level input voltage v il 0.8 v input voltage hysteresis 0.3 v off state output current -1 +1 a electrical characteristi cs for analog i/o pads parameter min max unit remarks pin name vport_posx operating voltage 44 62 v pin current consumption -5 +10 a port driver, vport measurement and ac generator are off pin name vport_negx operating voltage 0 vmain v pin current consumption -5 +10 a port driver, v port measurement and ac generator are off pin name vmain operating voltage ? af mode 40 57 v recommended range 48v to 55v operating voltage ? at mode 50 57 v recommended range 51v to 55v v main current consumption 40 ma total on v main pin name 3_3vout voltage 3.13 3.46 v 6 ma without external npn (see q1 in figure 8) output current 30 ma when using external npn for v peri (see q1 in figure 8 )
pd671xxx - 8 / 12 / 24-channel poe af and at dimm data sheet (non-confidential) copyright ? 2009 microsemi page 6 rev. 1.0 / 17-march-10 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; within the usa: (8 00) 713-4113, outside the usa: (949) 221-7100 fax: (949) 756-0308 www. microsemi . com pd671xx dimm dynamic characteristics____________ the pd671xxx dimms utiliz e three programmable current level thresholds (i min , i cut , i lim ) and two timers (t min , t cut ), to operate as shown in figure 4. loads that consume more than i cut for longer than t cut (ovl_s to ovl) are categorized as ?overloads? and are automatically shutdown. automatic recovery from overload and no-load conditions is attempted every t ovlrec and t udlrec periods (typically 5 and 1 seconds, respectively). ou tput current is limited to i lim, which is the maximum peak current allowed at each port. dc disconnect output current consumption below i min for more than t pmdo (udl_s to udl) is categorized as ?no-load? and is shutdown. ac disconnect a port maintains power if zac < 27 k a port shutdowns power if zac > 1980 k for a time period greater than tpmdo. parameter conditions min. typ. max. unit automatic recover y from t ovlrec value, measured from port shutdown ( can be modified via control p ort ) 5 s automatic recover y from no- t udlrec value, measured from port shutdown p oint ( can be modified via control p ort ) 1 s inrush current i inrsh for t = 50 ms, c load =180 uf max. 750 ma output current o p eratin g ran g e i port continuous operation after startup p eriod 10 700 ma output power available, operating range p port continuous operation after startup period, at port output (@ vport = 57 vdc) 0.57 30 w i min1 must disconnect for t greater than t uvl 0 5 ma dc disconnect off mode i min2 may or may not disconnect for t greater than t uvl 5 7.5 10 ma zac1 does not remove power 27 k ac disconnect off mode zac2 remove power 1980 k pd power maintenance t pmd buffer period to handle transitions 300 400 ms over load current detection ran g e i cut time limited to t ovl 660 680 700 ma over load time limit t ovl typical timer accuracy is 2 ms 50 75 ms turn on rise time t rise from 10% to 90% of v port (specified for pd load consistin g of 100 uf ca p acitor 15 us port turn off time toff from v port to 5 vdc 500 ms i lim i cut i min t min udl_s udl port off ovl t cut ovl_s i channel port 1 port 2 figure 4: power limits
pd671xxx - 8 / 12 / 24-channel poe af and at dimm data sheet (non-confidential) copyright ? 2009 microsemi page 6 rev. 1.0 / 17-march-10 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; within the usa: (8 00) 713-4113, outside the usa: (949) 221-7100 fax: (949) 756-0308 pd671xx dimm www. microsemi . com pin designations __________ the pd671xxx dimms have a fit/form based on a jedec mo-161f outline. conventions used in the design are as follows: ? power and ground connections are reproduced a number of times to carry heavy currents. ? signals are categorized as analog (input or output) or digital (input, output and i/o). ? all lines which are identified with an ?x? prefix are active when logical is low. refer to figure 5. figure 5: pinout
pd671xxx - 8 / 12 / 24-channel poe af and at dimm data sheet (non-confidential) copyright ? 2009 microsemi page 7 rev. 1.0 / 17-march-10 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; within the usa: (8 00) 713-4113, outside the usa: (949) 221-7100 fax: (949) 756-0308 pd671xx dimm www. microsemi . com pin description signals are categorized as ?analog? (input or output) or ?digital? (input, output and i/o). pin pin name pin type pin description pin pin name pin type pin description 1 85 2 86 3 87 4 88 5 89 6 vmain main v+ input 90 vmain main v+ input 7 91 8 92 9 93 10 94 11 95 12 vmain_ret power input main v return 96 vmain_ret power input main v return 13 port_p0 channel 1 positive output 97 14 port_n0 channel 1 negative output 98 15 port_p1 channel 2 positive output 99 16 port_n1 channel 2 negative output 100 17 port_p2 channel 3 positive output 101 18 port_n2 channel 3 negative output 102 19 port_p3 channel 4 positive output 103 20 port_n3 channel 4 negative output 104 21 port_p4 channel 5 positive output 105 22 port_n4 channel 5 negative output 106 23 port_p5 channel 6 positive output 107 24 port_n5 channel 6 negative output 108 25 port_p6 channel 7 positive output 109 26 port_n6 channel 7 negative output 100 27 port_p7 channel 8 positive output 111 28 port_n7 channel 8 negative output 112 spare 29 port_p8 channel 9 positive output 113 tbd tbd 30 port_n8 channel 9 negative output 114 tbd tbd 31 port_p9 channel 10 positive output 115 tbd tbd 32 port_n9 channel 10 negative output 116 tbd tbd 33 port_p10 channel 11 positive output 117 i2c_addr_0 digital input a uto mode; sets i2c address 34 port_n10 channel 11 negative output 118 qgnd0 ground quiet ground 35 port_p11 channel 12 positive output 119 cp_0 analog output nc (not in use) 36 port_n11 analog output channel 12 negative output 120 asicini_6_ out 37 tbd tbd 121 asicini_7_ out analog output determine dimm 4 managers espi address 38 tbd tbd 122 xexist digital output grounded internally- dimm is present 39 asicini_4_ out 123 ext_reg analog output external regulation for 3.3 v 40 asicini_5_ out analog output determine dimm 3 managers espi address 124 3_3vout analog output 3.3 v output to support opto couplers (5 v tolerant) 41 xled_cs digital output cs for led support 125 xhswp_on digital output connect to mcu 42 tbd tbd 126 dgnd ground digital ground 43 bkgd digital input factory use only 127 sck digital i/o spi clock ? pd69012 internal comm 44 dgnd ground digital ground 128 miso digital i/o spi i/o ? pd69012 internal comm 45 xasic_reset digital i/o internal reset to pd69012 129 mosi digital i/o spi i/o ? pd69012 internal comm 46 xreset_in digital input a reset signal driven by the host cpu to poe dimm 130 asicini_0_ in analog input determine dimm managers espi address 47 asicini_0_ out analog output determine dimm 1 manager espi address 131 asicini_1_ in analog input determine dimm managers espi address 48 asicini_1_ out analog output determine dimm 1 managers espi address 132 cs0 digital i/o cs for espi 49 asicini_2_ out analog output determine dimm 2 managers espi address 133 dgnd ground digital ground
pd671xxx - 8 / 12 / 24-channel poe af and at dimm data sheet (non-confidential) copyright ? 2009 microsemi page 8 rev. 1.0 / 17-march-10 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; within the usa: (8 00) 713-4113, outside the usa: (949) 221-7100 fax: (949) 756-0308 pd671xx dimm www. microsemi . com pin pin name pin type pin description pin pin name pin type pin description 50 asicini_3_ out 134 rx digital input uart input 51 hw_ver_in analog input receives the hardwar e version 135 tx digital output uart output 52 hw_ver_out analog output reports on the hardware version 136 xint_in digital input nc (not in use) 53 pg1 digital input indicates ps 1 is good; low= ps bad. 137 xint_out digital output interrupt out signal 54 pg2 digital input indicates ps 2 is good; low= ps bad. 138 espi_cs digital i/o cs for espi between dimms 55 i2c_addr_m analog input enhanced mode ? sets i2c address 139 xdisable_port s digital input low=disable from host 56 tbd tbd 140 xsystem_ok digital output main dc input status indicator; low = vmain is out of range. 57 scl digital i/o i2c clock 141 sda digital i/o i2c data 58 dgnd ground digital ground 142 dgnd ground digital ground 59 rx2 digital input nc (not in use) 143 pg3 digital input indicates ps 3 is good, low= p s bad 60 tx2 digital output nc (not in use) 144 tbd tbd 61 port_p12 analog output channel 13 positive output 145 cp_1 analog output nc (not in use) 62 port_n12 analog output channel 13 negative output 146 tbd tbd 63 port_p13 channel 14 positive output 147 i2c_addr_1 digital input auto mode; sets i2c address 64 port_n13 channel 14 negative output 148 qgnd1 ground quiet ground 65 port_p14 channel 15 positive output 149 tbd tbd 66 port_n14 channel 15 negative output 150 tbd tbd 67 port_p15 channel 16 positive output 151 tbd tbd 68 port_n15 channel 16 negative output 152 tbd tbd 69 port_p16 channel 17 positive output 153 tbd tbd 70 port_n16 channel 17 negative output 154 71 port_p17 channel 18 positive output 155 72 port_n17 channel 18 negative output 156 73 port_p18 channel 19 positive output 157 74 port_n18 channel 19 negative output 158 75 port_p19 channel 20 positive output 159 76 port_n19 channel 20 negative output 160 77 port_p20 channel 21 positive output 161 78 port_n20 channel 21 negative output 162 79 port_p21 channel 22 positive output 163 80 port_n21 channel 22 negative output 164 81 port_p22 channel 23 positive output 165 82 port_n22 channel 23 negative output 166 83 port_p23 channel 24 positive output 167 84 port_n23 channel 24 negative output 168 spare
pd671xxx - 8 / 12 / 24-channel poe af and at dimm data sheet (non-confidential) copyright ? 2009 microsemi page 9 rev. 1.0 / 17-march-10 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; within the usa: (8 00) 713-4113, outside the usa: (949) 221-7100 fax: (949) 756-0308 pd671xx dimm www. microsemi . com functional description______ __________________ ____________ the following sections detail the pd671xxx dimm master functions. system level figure 6 illustrates a 24-port enhanced mode system based on the pd671xxx dimm master. figure 6: pd67124m/s dimm configuration figure 7 illustrates a 24-port auto mode sy stem based on the pd671xxx dimm master. figure 7: pd67124am/as dimm configuration enhanced dimm pd67124am isolation i/o pd (1 of 24) host cpu master ethernet switch poe system i 2 c spi bus pd (25 of 48) enhanced dimm pd67124as slave pd69012 pd69012 pd69012 pd69012 control lines control lines enhanced dimm pd67124m isolation i/o pd (1 of 24) host cpu master ethernet switch poe system uart / i 2 c spi bus pd (25 of 48) enhanced dimm pd67124s slave pd69012 pd69012 pd69012 pd69012 control lines control lines poe controller pd69000
pd671xxx - 8 / 12 / 24-channel poe af and at dimm data sheet (non-confidential) copyright ? 2009 microsemi page 10 rev. 1.0 / 17-march-10 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; within the usa: (8 00) 713-4113, outside the usa: (949) 221-7100 fax: (949) 756-0308 pd671xx dimm www. microsemi . com enhanced mode pd671xxx dimm block diagram figure 8 illustrates the internal circuitry of the enhanc ed mode dimm master. pd69012 appears only in one of the 12 port circuits. figure 8: pd67124m dimm, internal block diagram top assembly description the following sections detail the top assembly components. power supply the entire circuit is powered by a nominal 48 vdc potential (vmain can range from 44 to 57 vdc for af mode and 50 to 57 vdc for at high power mode). 3.3 vdc regulator each of the pd69012 includes a 3.3 vdc regulator ( ext_reg and 3_3vout ) for up to 6 ma. this current is utilized for power ing external components in the poe domain. there is an option of adding a driver to this output to drive higher loads. q1 provides up to 30 ma to the poe controller and to the opto-couplers in the interface circuit. the total capacitance on the 3.3 vdc should be less then 4.7 uf (with and without an external driver). grounds the overall circuit includes two physical ground planes, analog and digital, which are electrically connected at a single point on the motherboard (see figure 9 and figure 10). this method, used throughout the design, improves noise immunity and coupling. application note an-132, catalogue number 06-0010-080 provides further details about this design technique. control signals several control signals are utilized between the switch and the poe circuitry: ? xreset_in: driven by the switch circuitry to reset the poe circuit. ? xdisable_ports : driven by the switch, to disable all poe ports immediately. indication signals ? int_out: enables the host cpu to reduce the communication volume whenever a poe event masked by the host cpu occurs. the poe controller sends an interrupt for indication. ? system_ok: (enhanced mode only) an optional hardware single line, driven by the master dimm to the host cpu; this signal provides the host cpu with a warning that a major failure such as vmain out of range has occurred.
pd671xxx - 8 / 12 / 24-channel poe af and at dimm data sheet (non-confidential) copyright ? 2009 microsemi page 11 rev. 1.0 / 17-march-10 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; within the usa: (8 00) 713-4113, outside the usa: (949) 221-7100 fax: (949) 756-0308 pd671xx dimm www. microsemi . com pd69012 circuitry all pd69012s work in slave mode, under control of the pd69000g. the poe managers, each controlling 12 output ports, are further detailed in figure 8. the ports can be disabled by the ethernet switch via the xdisable_ports signal or by the poe controller, as required during operation. for further details on the poe manager, refer to the poe manager pd69012 data sheet, catalogue number 06-0072-058. ac disconnect diodes when deploying an application that utilizes the ac disconnect method, carefully select the diode type and diode location on the mother board. the diode should be located away from the dimm to prevent mutual heating and the ventilation should be doubled to deal with higher power dissipation. the ac disconnect diode should be connected as shown in figure 9. dc disconnect using the dc disconnect method, the mother board should contain a short circuit between vmain coming from the power supply and port_p[0-23] as illustrated in figure 10. pd671xxx dimm evaluation board __________________ the performance features of microsemi?s poe dimms can be fully appreciated using the pd671xxx - dimm evaluation board. the evaluation board allows the designer to evaluate all of the dimms accessible functions. enhanced mode configuration for up to 48 ports is supported. applications_______________ the dimms can be integrated into a number of applications, ranging from daughter boards to full integration into ethernet switches. examples of such applications are as follows: ? integrated directly into a switch : facilitates the entire poe concept by including the dimms on the main switch pcb. ? daughter board add-on : dimms are integrated into a small pcb for poe, mounted on top of the switch?s main pcb. ? midspan units : stand-alone devices, installed between the ethernet switch and powered devices (telephone, camera, wireless lan, etc.). these midspan units include the dimms as a poe control element, injecting power over the communication lines. figure 9: overall pd671xxx dimm at ac disconnect wiring diagram figure 10: overall pd671xxx dimm at dc disconnect wiring diagram
pd671xxx - 8 / 12 / 24-channel poe af and at dimm data sheet (non-confidential) copyright ? 2009 microsemi page 12 rev. 1.0 / 17-march-10 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; within the usa: (8 00) 713-4113, outside the usa: (949) 221-7100 fax: (949) 756-0308 pd671xx dimm www. microsemi . com power dissipation_________ __________________ ___________ the pd671xxx power dissipation is concentrated with in a few components distri buted along the board as follows. these power dissipation calculations ar e based on a 24 port dimm supplied by a 48 vdc power supply and located at ambient temperature of 70 c. power dissipation [w] component description units ieee802.3af 0.35a/port ieee802.3at 0.6a/port ieee802.3at 0.65a/port rs senses resistor 24 1.43 4.21 4.94 mosfet poe switching mosfet 24 0.56 1.64 1.93 pd69012 poe manager 2 1.15 1.15 1.15 pd69000 poe controller 1 * 0.02 0.02 0.02 total 3.16 7.02 8.04 * enhanced mode master board only important : when deploying an application utilizing the ac disc onnect method, carefully select the diode type and diode location on the mother board. the diode should be located away from the dimm to prevent mutual heating and the ventilation should be doubled to deal with higher power dissipation. ac disconnect diodes power dissipation is based on 1 vdc forward voltage. power dissipation [w] component description units ieee802.3af 0.35a/port ieee802.3at 0.6a/port ieee802.3at 0.65a/port diode ac disconnect diode 24 8.4 14.4 15.6 physical information __ __________________ _______________ figure 11 shows the pd671xxx dimm mechanical outline, whic h can be used in printed circuit layout design. pd671xxx dimms are designed to be mounted onto a 168- contact dimm connector, capable of accepting jedec mo-161 modules. all units are in millimeters. figure 11: dimm dimensions figure 12: mechanical outline of the pd671xxx dimm
pd671xxx - 8 / 12 / 24-channel poe af and at dimm data sheet (non-confidential) copyright ? 2009 microsemi page 13 rev. 1.0 / 17-march-10 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; within the usa: (8 00) 713-4113, outside the usa: (949) 221-7100 fax: (949) 756-0308 pd671xx dimm www. microsemi . com revision history revision level / date para. affected description 0.1 / oct. 1 , 2009 initial release 0.2 / oct. 29 , 2009 overall doc 1.0 / 17-march-10 formal release ? 2009 microsemi corp. all rights reserved. for support contact: sales_amsg@microsemi.com visit our web site at: www.microsemi.com catalogue number: 06-0021-058

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